1. Field of Invention
The invention relates to a design flow method, and more particularly, to a circuit design flow method that generates DFT (Design For Test) scan chains for IC implementation.
2. Background of the Invention
The circuit system design of the very large-scale integrated circuit (VLSI) is usually achieved using components provided by a circuit module database. The flow of the IC design contains selecting correct modules and connecting related modules to provide needed functions. The processes for defining the modules are closely related to a database comprising standard cells. Even a small improvement can result in great help in lowering manufacturing costs and enhancing the effects.
Please refer to FIG. 1, which illustrates the links of a scan chain 101 in a circuit module 100. The circuit module 100 is part of a circuitry. In other words, a VLSI includes one or more circuit modules 100. There are functional connections among these modules to provide the circuit functions claimed in the specification. After the designer follows the specification and completes the functional design of the circuit system, the flow procedure often includes the generation of DFT (Design For Test) circuits, such as the test controller 107, for performing verification for the circuit module 100 in subsequent manufacturing processes.
The circuit module 100 includes an isolating scan chain 103 positioned at the boundary of the circuit module, one or more internal scan chains and control bit scan chains, e.g. scan chains 101, 102. These scan chains form isolation ring circuits. Test patterns are loaded from one or more of the scan-in terminals 104. The data in the circuits of the scan chains can be read through one or more than one scan-out terminal 105 to test whether the functions of the circuit module 100 are correct.
FIG. 2 illustrates a conventional IC design flow procedure. The flow contains the procedure to generate the scan chains for testing each circuit module.
To design a complete IC in a normal design flow, it is necessary to first accomplish the circuit design procedure 201 for the IC. This circuit design procedure includes a complete function description described by HDL (Hardware Description Language), e.g. the design description interfaces such as VHSIC (Very High Speed Integrated Circuit) or Verilog, is employed to present a function description for the circuit design. Such description includes the declaration of input and output signals, the internal structure and the behaviors of the circuit. After the circuit design procedure 201 is completed, a synthesis procedure 202 is started to convert the completed circuit modules into the actual gate levels. These gates may be such basic logic gates as AND, OR, and NOR gates, and they constitute the whole circuit. The synthesis procedure includes a DFT synthesis procedure for generating some cells in the circuit module and forming the scan chains. After the synthesis procedure 202 is completed, a pre-simulation procedure 203 is started before placement and routing. The pre-simulation procedure 203 is used to verify whether the designed circuit module and its scan chain timing have any error. If any error happens, the designer has to go back to the circuit design procedure 201 to modify the circuit module again. Such procedures have to be repeated until the timing of the circuit module passes the verification.
However, the pre-simulation procedure 203 takes the circuit component symbols of the converted actual gates and converts them into a circuit analysis simulation program. At this stage, the circuit analysis simulation program can only make a rough estimations for the timing because it does not contain the information of placement and routing. That is, the simulation does not contain the information of actual wire delay and cell delay. It only analyzes whether the circuit behaviors meet the functions of the specification.
After performing the pre-simulation procedure 203 and verifying that there is no error, a placement & routing procedure 204 is initiated. Once the placement & routing procedure 204 is completed, the information of the circuit module placement and the wire lengths inside the IC is fixed. At this moment, a program is used to check whether there is any mistake in the placement and routing. This is the post-simulation procedure 205. The simulation result of the post-simulation procedure 205 will be compared with the previous simulation result to see if they are consistent. If they are, then a manufacturing procedure 206 is performed; otherwise, one has to analyze such practical issues as wire delays or cell delays. The designer has to modify the circuit simulation analysis software or change the original functions of the circuit module. The placement & routing procedure 204 or the circuit design procedure 201 has to be done again until the final simulation results satisfy the specification. Apparently, this procedure waste too much time in going back and forth among different steps.
The conventional IC design process is tediously long. The purpose of inserting the DFT synthesis procedure into the synthesis procedure 202 is to test the IC products. Therefore, when the DFT synthesis procedure 202 is implemented before the placement & routing procedure 204 is carried, the generated scan chain does not take into account the information of circuit placement and routing. The results from the pre-simulation procedure 203 cannot accurately reflect the actual timing, but just a rough estimation. Consequently, the results from the post-simulation procedure 205 often have timing violation.
VLSI has to be tested to make sure that the chips do not contain fatal errors during the manufacture. The test process applies many test vectors for the VLSI and each test vector explicitly specifies the input signal for different input circuits. Suppose the circuit is in operation, the test controller makes a decision according to the output from the test circuit. As the circuit becomes complicated, the number of test vectors also increases in order to make comprehensive circuit tests. This inevitably makes the test processes too costly. Moreover, the market competition also imposes a limit on the time for a design engineer to finish the circuit design. Since the design time is forced to be shorter, the time that can be used for timing and function verification is also sacrificed. The above-mentioned factors form the bottleneck of the verification task. Therefore, the chip designers are pushed to find a new verification method to increase the efficiency.
When a chip is found to have a defect, it is still possible to fix the problem if the location of the error can be identified. For example, some chip designs use a long module connected to a bus to substitute a non-operating module that is connecting to the bus. It is of great value to find out the error during the production process by testing each module.